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preliminary rev. 0.6 7/13 copyright ? 2013 by silicon laboratories SI535/536 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI535/536 u ltra l ow j itter c rystal o scillator (xo) features applications description the SI535/536 xo utilizes silicon laboratories? advanced dspll ? circuitry to provide an ultra low jitter clock at high-speed differential frequencies. unlike a traditional xo, where a different crystal is required for each output frequency, the SI535/536 uses one fixed crystal to provide a wide range of output frequencies. this ic based approach allows the crystal resonator to provide exceptional frequency stability and reliability. in addition, dspll clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. the SI535/536 ic based xo is factory programmed at time of shipment, thereby eliminat ing long lead times associated with custom oscillators. functional block diagram ? available with select frequencies from 100 mhz to 312.5 mhz ? 3rd generation dspll ? with superior jitter performance and high-power supply noise rejection ? 3x better frequency stability than saw-based oscillators ? available with lvpecl and lvds outputs ? 3.3 and 2.5 v supply options ? industry-standard 5 x 7 mm package and pinout ? pb-free/rohs-compliant ? 10/40/100g data centers ? 10g ethernet switches/routers ? fibre channel/sas/storage ? enterprise servers ? networking ? telecommunications fixed frequency xo 100?312.5 mhz dspll ? clock synthesis v dd clk+ clk? oe gnd ordering information: see page 7. pin assignments: see page 6. (top view) si5602 1 2 3 6 5 4 gnd oe v dd clk+ clk? nc 1 2 3 6 5 4 gnd nc v dd clk+ clk? oe SI535 si536 r evision d free datasheet http:///
SI535/536 2 preliminary rev. 0.6 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit supply voltage 1 v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 v supply current i dd output enabled lvpecl lvds ? ? 111 90 121 98 ma tristate mode ? 60 75 ma output enable (oe) 2 v ih 0.75 x v dd ?? v v il ??0.5 v operating temperature range t a ?40 ? 85 c notes: 1. selectable parameter specified by part number. see section 3. "ordering information" on page 7 for further details. 2. oe pin includes a 17 k ? pullup resistor to v dd . table 2. clk output frequency characteristics parameter symbol test condition min typ max unit nominal frequency 1 f o lvpecl/lvds 100 ? 312.5 mhz initial accuracy f i measured at +25 c at time of shipping ? 1.5 ? ppm temperature stability 1,2 ?7 ?20 ? ? +7 +20 ppm aging f a frequency drift over first year ? ? 3 ppm frequency drift over 20 year life ? ? 10 ppm total stability 2 temp stability = 20 ppm ? ? 31.5 ppm temp stability = 7 ppm ? ? 20 powerup time 3 t osc ??10ms notes: 1. see section 3. "ordering information" on page 7 for the list of available frequencies. 2. selectable parameter specified by part number. 3. time from powerup or tristate mode to f o .
SI535/536 preliminary rev. 0.6 3 table 3. clk output levels and symmetry parameter symbol test condition min typ max unit lvpecl output option 1 v o mid-level v dd ? 1.42 ? v dd ? 1.25 v v od swing (diff) 1.1 ? 1.9 v pp v se swing (single-ended) 0.55 ? 0.95 v pp lvds output option 2 v o mid-level 1.125 1.20 1.275 v v od swing (diff) 0.5 0.7 0.9 v pp rise/fall time (20/80%) t r, t f ??350ps symmetry (duty cycle) sym differential 45 ? 55 % notes: 1. 50 ? to v dd ? 2.0 v. 2. r term = 100 ? (differential).
SI535/536 4 preliminary rev. 0.6 figure 1. SI535/536 typical phase noise at 156.25 mhz table 4. clk output phase jitter parameter symbol test condition min typ max unit lvpecl/lvds phase jitter* (rms) ? j 10 khz to 1 mhz (data center) ? 0.19 ? ps 12 khz to 20 mhz (oc-48) ? 0.25 ? ps *note: applies to output frequencies: 156.25 mhz. table 5. clk output period jitter parameter symbol test condition min typ max unit lvpecl/lvds period jitter* j per rms ? 2 ? ps peak-to-peak ? 14 ? ps *note: n = 1000 cycles.
SI535/536 preliminary rev. 0.6 5 table 6. environmental compliance the SI535/536 meets the following qualification test requirements. parameter conditions/test method mechanical shock mil-std-883, method 2002 mechanical vibration mil-std-883, method 2007 solderability mil-std-883, method 2003 gross & fine leak mil-std-883, method 1014 resistance to solder heat mil-std-883, method 2036 moisture sensitivity level j-std-020, msl1 contact pads gold over nickel table 7. thermal characteristics (typical values ta = 25 oc, v dd =3.3v) parameter symbol test condition min typ max unit thermal resistance junction to ambient ? ja still air ? 84.6 ? c/w thermal resistance junction to case ? jc still air ? 38.8 ? c/w ambient temperature t a ?40 ? 85 c junction temperature t j ??125c table 8. absolute maximum ratings 1 parameter symbol rating unit maximum operating temperature t amax 85 c supply voltage, 2.5/3.3 v option v dd ?0.5 to +3.8 v input voltage (any input pin) v i ?0.5 to v dd + 0.3 v storage temperature t s ?55 to +125 c esd sensitivity (hbm, per jesd22-a114) esd 2500 v soldering temperature (pb-free profile) 2 t peak 260 c soldering temperature time @ t peak (pb-free profile) 2 t p 20?40 seconds notes: 1. stresses beyond those listed in absolute maximum ratings may cause permanent damage to the device. functional operation or specification co mpliance is not implied at these conditions. exposure to maximum rating conditions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020c. refer to si5xx packaging faq available for download at www.silabs.com/vcxo for further information, including soldering profiles.
SI535/536 6 preliminary rev. 0.6 2. pin descriptions table 9. pinout for SI535 series pin symbol function 1 nc no connection 2oe output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 3 gnd electrical and case ground 4 clk+ oscillator output 5 clk? complementary output 6v dd power supply voltage *note: oe includes a 17 k ? pullup resistor to v dd . table 10. pinout for si536 series pin symbol function 1oe output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 2 no connection no connection 3 gnd electrical and case ground 4 clk+ oscillator output 5 clk? complementary output 6v dd power supply voltage *note: oe includes a 17 k ? pullup resistor to v dd . (top view) 1 2 3 6 5 4 gnd oe v dd clk+ clk? nc 1 2 3 6 5 4 gnd nc v dd clk+ clk? oe SI535 si536
SI535/536 preliminary rev. 0.6 7 3. ordering information the SI535/536 xo su pports a variety of options incl uding frequency, temp erature stability, ou tput forma t, and v dd . the SI535 and si536 xo series are supplied in an indu stry-standard, rohs complia nt, 6-pad, 5 x 7 mm package. the si536 series supports an alternate oe pinout (pin #1 ) for the lvpecl and lvds outp ut formats. see tables 9 and 10 for the pinout differences between the SI535 and si536 series. figure 2. part number convention 53x x xxxmxxx x 1 st option code v dd output format output enable polarity a 3.3 lvpecl high b 3.3 lvds high e 2.5 lvpecl high f2.5lvds high d g r tape & reel packaging blank = trays operating temp range (c) g -40 to +85 c device output enable 535 pin 2 536 pin 1 example p/n: 535ab156m250dgr is a 5 x 7 xo in a 6 pad package. the frequency is 156.250 mhz, with a 3.3 v supply, lvpecl outpu t, and output enable active high polarity. temperature stability is specifed as 20 ppm. the part is specified for ?40 to +85 c ambient temperature range operation and is shipped in tape and reel format. 2 nd option code code temperature stability (ppm, max, ) total stablility (ppm, max, ) b 20 31.5 c 7 20 frequency (e.g., 156m250 is 156.250 mhz) select frequencies available in the frequency range 100 to 312.5 mhz are listed below. frequencies requiring greater than 6 digit resolution are assigned a six digit code. part revision letter available ? frequencies frequency ? order ? code 106.250 ? mhz 106m250 125.000 ? mhz 125m000 150.000 ? mhz 150m000 155.520 ? mhz 155m520 156.250 ? mhz 156m250 156.2578 ? mhz 000305 156.2539 ? mhz 000335 159.375 ? mhz 159m375 161.1328 ? mhz 000174 166.6286 ? mhz 000118 167.3316 ? mhz 000119 212.500 ? mhz 212m500 312.500 ? mhz 312m500
SI535/536 8 preliminary rev. 0.6 4. package outline figure 3 illustrates the package details fo r the SI535/536. table 11 lists the val ues for the dimensio ns shown in the illustration. figure 3. SI535/536 outline diagram table 11. package diagram dimensions (mm) dimension min nom max a 1.50 1.65 1.80 b 1.30 1.40 1.50 c 0.50 0.60 0.70 d 5.00 bsc d1 4.30 4.40 4.50 e 2.54 bsc e 7.00 bsc e1 6.10 6.20 6.30 h 0.55 0.65 0.75 l 1.17 1.27 1.37 p 1.80 ? 2.60 r 0.70 ref aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05
SI535/536 preliminary rev. 0.6 9 5. 6-pin pcb land pattern figure 4 illustrates the 6-pin pcb land pa ttern for the SI535/ 536. table 12 lists the values for the dimensions shown in the illustration. figure 4. SI535/536 pcb land pattern table 12. pcb land pattern dimensions (mm) dimension min c1 4.20 e2.54 x1 1.55 y1 1.95 notes: general 1. all dimensions shown are in m illimeters (mm) unle ss otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 1. all metal pads are to be non-solder mask defined (nsmd). cl earance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil wit h trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec /ipc j-std-020d specification for small body components. ?
SI535/536 10 preliminary rev. 0.6 6. SI535/si536 ma rk specification figure 5 illustrates the mark specif ication for the SI535/si536. ta ble 13 lists the line information. figure 5. mark specification table 13. si53x top mark description line position description 1 1?10 ?silabs"+ part family numb er, 53x (first 3 characters in part number where x = 5 indicates a 535 device and x = 6 indicates a 536 device). 2 1?10 SI535, si536: option1 + option2 + freq(7) + temp SI535/si536 w/ 8-digit resolution: option1 + option2 + confignum(6) + temp 3 trace code position 1 pin 1 orientation mark (dot) position 2 product revision (d) position 3?6 tiny trace code (4 alphanumeric characters per assembly release instructions) position 7 year (least significant year digit), to be assigned by assembly site (ex: 2013 = 3) position 8?9 calendar work week number (1?53), to be assigned by assembly site position 10 ?+? to indicate pb-free and rohs-compliant ?
SI535/536 11 preliminary rev. 0.6 d ocument c hange l ist revision 0.2 to revision 0.3 ? updated table 7 on page 5. revision 0.3 to revision 0.5 ? updated note 1 in table 2 on page 2. ? updated symmetry test condition in table 3 on page 3. ? updated table 4 on page 4. ? updated table 5 on page 4. ? updated xxxmxxx text in figure 2 on page 7. ? updated 4. "package outline" on page 8. revision 0.5 to revision 0.6 ? updated figure 2 on page 7. ? updated land pattern information on page 10.
SI535/536 12 preliminary rev. 0.6 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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